The present invention relates to the field of non-volatile memory devices such as electrically erasable programmable read-only memories (EEPROMs), and flash memories. More specifically, the present invention relates to a method and apparatus for improving charge retention in floating gate devices in non-volatile memory device cells.
Charge retention is an important characteristic of reliable non-volatile memory devices. The oxide surrounding the polysilicon of the floating gate device of a non-volatile memory cell serves as an insulator for preventing charge loss. Damage to oxide surrounding the polysilicon of floating gate devices has been associated with charge loss in non-volatile memory devices. Damage to the oxide may result, for example, from the actual doping of the oxide and/or from an increased chemical doping level of the polysilicon next to the oxide.
In the past, the application of a hard mask oxide was used to minimize damage to the oxide surrounding floating gate devices. The hard mask minimized damage on the oxide by isolating both the oxide and the polysilicon from doping processes such as those used for source drain implantation. Current salicide processes, however, utilize a layering process which involve application of a metal, such as titanium, over the polysilicon in order to lower the resistive properties of the polysilicon. This process prevents the application of the hard mask.
Thus, what is needed is a method and apparatus for addressing the problem of oxide damage along the polysilicon gate.
A method and apparatus for reducing charge loss in a non-volatile memory cell is disclosed. A region forming a floating polysilicon structure in the non-volatile memory cell is selectively blocked during a doping process. The floating polysilicon structure may be selectively blocked by using a layer of photoresist, oxide, or other dopant blocking material. By selectively blocking a region forming the floating polysilicon structure, damage to the oxide that operates as an insulator for the floating polysilicon structure may be minimized. The region that is blocked may be an entire floating polysilicon layer or an outer edge of the floating polysilicon layer.
A method of fabricating a non-volatile memory cell on a semiconductor substrate according to a first embodiment of the present invention is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.
A method of fabricating a non-volatile memory cell on a semiconductor substrate according to a second embodiment of the present invention is disclosed. A chemical polysilicon doping level of components in a floating polysilicon region of the semiconductor substrate is varied with a chemical polysilicon doping level of components in a non-floating polysilicon region of the semiconductor substrate.
A non-volatile memory cell according to an embodiment of the present invention is disclosed. The non-volatile memory cell includes a floating gate device, coupling gate capacitor, and tunneling capacitor having a first level of polysilicon doping. The non-volatile memory cell includes select transistors with a second level of polysilicon doping.